EDN

Is static timing analysis still valid?

SAN MATEO, Calif. — Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected. But this vital technique itself rests upon assumptions that may no ...
Semiconductor Engineering

The Demise Of Static Timing Verification?

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...
Design-Reuse

IP Verification : Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...
Electronic Design

Using Timing Constraints For Generating At-Speed Test Patterns

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...